1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices and more particularly to a nonvolatile semiconductor memory device using trench isolation. The present invention also relates to a method of manufacturing such a nonvolatile semiconductor memory device.
2. Description of the Background Art
FIG. 6 is a plan view of a conventional nonvolatile semiconductor memory device using trench isolation. FIG. 7 shows a cross section (A) along the line Axe2x80x94A of FIG. 6, and a cross section (B) along the line Cxe2x80x94C of FIG. 6.
Referring to these figures, the conventional nonvolatile semiconductor memory device includes a semiconductor substrate 1. In a main surface of semiconductor substrate 1, a linear trench 2 for trench isolation is formed in the direction Y of bit lines. An insulation film 24 for trench isolation is filled in trench 2. Trench 2 and insulation film 24 filled therein constitute a trench isolation region. On both sides of trench 2, a floating gate 4 is provided on semiconductor substrate 1 with a tunnel oxide film 3 therebetween. On floating gate 4, a control gate 6 is provided with an inter poly-insulation film 5 therebetween.
Referring next to FIG. 8, the operation of the nonvolatile semiconductor memory device will be described.
Here, the Fowler-Nordheim tunnel current writing method at a memory drain edge and the Fowler-Nordheim tunnel current erasing method on the entire channel surface, which are common to DINOR type flash memories, will be described.
Whether information is stored or not is determined by the charged and discharged states of a floating gate. When a floating gate is injected with electrons and negatively charged, Vth becomes higher with respect to the potential of a control gate thereon (erased state). When the floating gate is not negatively charged, however, Vth is low (written state). By applying, to the control gate, an intermediate voltage between Vth in the erased state and Vth in the written state, stored contents can be read through a memory cell transistor.
Writing can be performed on a basis of a bit by selecting a sub bit line (drain interconnection) and a word line (gate interconnection). Since an erase voltage can be applied on a basis of a word line (gate interconnection), erasing can be performed on a basis of a sector.
Since a floating gate electrode is covered by a high quality insulation film, injected electrons remain in the electrode unless erased. Accordingly, stored contents are maintained even if the power supply is turned off.
A conventional method of manufacturing the nonvolatile semiconductor memory device using trench isolation will be described in the following with reference to the figures.
In the figures described hereinafter, cross sections on the left side correspond to the cross section along the line Axe2x80x94A of FIG. 6, and those on the right side correspond to the cross section along the line Cxe2x80x94C.
Referring to FIG. 9, a surface of semiconductor substrate (silicon substrate) 1 is oxidized to form tunnel insulation film 3 which is approximately 100 nm in film thickness. On tunnel insulation film 3, a polysilicon film 7 or amorphous silicon film (approximately 200 nm) doped with an n type impurity such as phosphorus, and a CVD oxide film 8 (approximately 100 nm) are successively deposited.
Referring to FIG. 10, a resist pattern 9 is formed by photo lithography, which has openings in portions in which first and second trenches extending in parallel with each other in the bit line direction are to be formed. Referring to FIGS. 9 and 10, resist pattern 9 is used for patterning in the bit line direction, oxide film 8, polysilicon film 7 and tunnel oxide film 3 are etched in this order, and trench 2 which is approximately 500 nm in depth is formed in the surface of semiconductor substrate 1. Thus, trench 2 is formed in a self-alignment manner with an uncompleted floating gate 4. Then, resist pattern 9 and oxide film 8 are removed.
Referring to FIGS. 10 and 11, a CVD insulation film 24 such as tetraethoxysilane (TEOS) is filled in trench 2. CVD insulation film 24 is etched to the surface of semiconductor substrate 1 such as by chemical mechanical polishing (CMP) to form uncompleted floating gate 4 which extends in the bit line direction. Then, an ONO film (thin laminate film formed of a CVD oxide film of approximately 5 nm/a CVD nitride film of approximately 5 nm/a CVD oxide film of approximately5 nm) 5 is formed to cover floating gate 4.
Referring to FIG. 12, polysilicon 13 (approximately 50 nm) doped with an n type impurity such as phosphorus, a refractory metal silicide 14 (approximately 50 nm) such as WSi, and a CVD oxide film 15 (approximately 100 nm) such as TEOS are successively deposited. On CVD oxide film 15, a resist pattern 16 for forming a control gate is formed.
Referring to FIGS. 12 and 13, CVD oxide film 15, refractory metal silicide 14, polysilicon 13, ONO film 5, and uncompleted floating gate 4 are etched in this order to complete floating gate 4 and control gate 6.
Referring to FIG. 14, a portion other than a region to be a drain region is masked by a resist pattern 17 and subjected to ion implantation to form a drain region 18.
Referring to FIGS. 15 and 16, a portion other than a region to be a source region is masked and subjected to ion implantation to form a source region 19.
Referring to FIG. 17, a bit line 20 is formed, first and second Al interconnections 21 and 22 are formed thereon with interlayer insulation films 28 and 29 therebetween, and a glass coating 23 is formed. Thus, a memory cell transistor is completed.
Since the conventional method of manufacturing the nonvolatile semiconductor memory device is as described above, problems occur as described below.
In FIG. 18, (A) and (B) are cross sections along the lines Axe2x80x94A and Bxe2x80x94B of FIG. 6 in the step of FIG. 13 (a bit line contact is omitted herein).
Referring to FIGS. 18 and 13, when the trench formed in a self-alignment manner with floating gate 4 is used for isolation, problems occur in etching control gate (memory gate) 6 and also etching uncompleted floating gate 4. That is, in the cross section along the line Bxe2x80x94B shown in (B) of FIG. 18, oxide film 24 for trench isolation in trench 2 may be etched, causing a side surface of semiconductor substrate 1, that is, a side surface of trench 2 (a portion 50 indicated by a circle in the figure) to be exposed. As described above, exposure of the side surface of semiconductor substrate 1 prevents isolation characteristics to be maintained sufficiently.
Referring to (A) of FIG. 18, there is also a problem of electric field concentration on inter poly-insulation film 5 between floating gate 4 and control gate 6 because an upper end of floating gate 4 (portion 51 indicated by a circle in the figure) is angular and sharp.
The present invention was made to solve the problems as described above, and its object is to provide an improved nonvolatile semiconductor memory device so as to be able to maintain isolation characteristics sufficiently.
Another object of the present invention is to provide an improved nonvolatile semiconductor memory device so as not to concentrate electric fields on an inter poly-insulation film between a floating gate and a control gate.
Further object of the present invention is to provide a method of manufacturing an improved nonvolatile semiconductor memory device so as to be able to maintain isolation characteristics.
Still another object of the present invention is to provide a method of manufacturing an improved nonvolatile semiconductor memory device so as not to concentrate electric fields on an inter poly-insulation film between a floating gate and a control gate.
A nonvolatile semiconductor memory device according to a first aspect of the present invention includes a semiconductor substrate. In a surface of the semiconductor substrate, first and second trenches, which extend in parallel with each other in a bit line direction, are provided. An oxide film for trench isolation is filled in the first and second trenches. Between the first and second trenches, a floating gate is provided on the semiconductor substrate. A sidewall spacer is provided on a sidewall surface, extending in the bit line direction, of the floating gate.
According to the present invention, the sidewall spacer is provided on the sidewall surface, extending in the bit line direction, of the floating gate, and therefore an angular portion of the floating gate is rounded, preventing concentration of electric fields on an inter poly-insulation film.
According to the nonvolatile semiconductor memory device in a second aspect of the present invention, the sidewall spacer is provided on sidewall surfaces, extending in the bit line direction, on both sides of the floating gate.
According to the nonvolatile semiconductor memory device in a third aspect of the present invention, the sidewall spacer is formed of polysilicon.
According to the nonvolatile semiconductor memory device in a fourth aspect of the present invention, an n type impurity is implanted in the polysilicon.
According to the nonvolatile semiconductor memory device in a fifth aspect of the present invention, the sidewall spacer increases in thickness from top to bottom.
According to the nonvolatile semiconductor memory device in a sixth aspect of the present invention, the sidewall surface, extending in the bit line direction, of the floating gate is coplanar with a sidewall surface of the trench.
According to the nonvolatile semiconductor memory device in a seventh aspect of the present invention, the oxide film for trench isolation is formed of a CVD insulation film of which material is TEOS.
In a method of manufacturing a nonvolatile semiconductor memory device according to an eighth aspect of the present invention, a tunnel insulation film and a first conductive layer are first successively formed on a semiconductor substrate. The first conductive layer and the tunnel insulation film are patterned in a bit line direction to form an uncompleted floating gate extending in the bit line direction and to form a trench in a surface of the semiconductor substrate in a self-alignment manner with the uncompleted floating gate. An insulation film for trench isolation is filled in the trench. A sidewall spacer is formed on a sidewall of the floating gate. On the semiconductor substrate, an insulation film and a second conductive layer are successively formed to cover the uncompleted floating gate. The second conductive layer, the insulation film and the uncompleted floating gate are patterned in a word line direction to form a completed floating gate and a control gate.
According to the present invention, the sidewall spacer is formed on the sidewall of the floating gate. Accordingly, a trench sidewall is not exposed even if the isolation insulation film in the trench is etched in etching the control gate (memory gate) and the uncompleted floating gate. As a result, a nonvolatile semiconductor memory device with isolation characteristics maintained is obtained.
According to the method of manufacturing a nonvolatile semiconductor memory device in a ninth aspect of the present invention, the sidewall spacer is formed of polysilicon.
In the method of manufacturing a nonvolatile semiconductor memory device in a tenth aspect of the present invention, the step of forming the sidewall spacer includes forming a polysilicon layer on the semiconductor substrate to cover the uncompleted floating gate, and carrying out isotropic etching of the polysilicon layer.
According to the method of manufacturing a nonvolatile semiconductor memory device in an eleventh aspect of the present invention, the insulation film is formed of a thin laminate film of an oxide film, a nitride film and an oxide film.
In the method of manufacturing a nonvolatile semiconductor memory device according to a twelfth aspect of the present invention, the insulation film for trench isolation is formed of a CVD oxide film of which material is TEOS.
In the method of manufacturing a nonvolatile semiconductor memory device according to a thirteenth aspect of the present invention, the first conductive layer is formed of a polysilicon layer or an amorphous silicon layer.
In the method of manufacturing a nonvolatile semiconductor memory device according to a fourteenth aspect of the present invention, the second conductive layer is formed of polysilicon.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.